
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Matiastop is
   port(     
      pulsador       : in  std_logic_vector(3 downto 0);    
      xtal           : in  std_logic;
      enable         : in  std_logic;
      Xin            : in  std_logic_vector(15 downto 0);
      Yin            : in  std_logic_vector(15 downto 0);
      Zin            : in  std_logic_vector(15 downto 0);
		vsinc_o	 		    : out std_logic;
		hsinc_o	 		    : out std_logic;
		red_o		  		   : out std_logic;
	   green_o	 		    : out std_logic;
	   blue_o	  		    : out std_logic
   );
	
	attribute LOC                 	: string;
   attribute LOC of xtal            : signal is "T9"; 
   attribute LOC of pulsador        : signal is "L14 L13 M14 M13";
   attribute LOC of hsinc_o 	      : signal is "R9";
   attribute LOC of vsinc_o 	      : signal is "T10";
   attribute LOC of red_o 	        	: signal is "R12";
   attribute LOC of green_o 	      : signal is "T12";
   attribute LOC of blue_o 	      : signal is "R11";

end Matiastop;

architecture Behavioral of Matiastop is

	component rotador3d is
		port(     
			pulsador         : in  std_logic_vector(5 downto 0);    
			xtal             : in  std_logic;
			enable           : in  std_logic;
			Xin              : in  std_logic_vector(15 downto 0);
			Yin              : in  std_logic_vector(15 downto 0);
			Zin              : in  std_logic_vector(15 downto 0);
			Yout             : out integer range 320 downto 0;
			Zout             : out integer range 320 downto 0;
			reset            : out std_logic
   );
	end component;
	component Mundo is
    port ( vsinc_o	 	: out std_logic;
	        hsinc_o	 	: out std_logic;
	        red_o		  	: out std_logic;
	        green_o	 	: out std_logic;
	        blue_o	  		: out std_logic;
	        reset    		: in std_logic;
	        Yin      		: in integer range 639 downto 0;
	 		  Zin      		: in integer range 479 downto 0;
	        xtal_i   		: in std_logic
	 );
	 end component;
	 component FF1b is
		port ( 
          clk: in std_logic;
          input: in std_logic;
          output: out std_logic
   	);
	end component;
	 

	 signal P 		: 	std_logic_vector (5 downto 0):="000000";
	 signal YR2M	:	integer range 320 downto 0;
	 signal ZR2M	:	integer range 320 downto 0;
	 signal rst		:	std_logic:='0';
	 signal l1		:	std_logic:='0';
	 signal l2		:	std_logic:='0';
	 signal l3		:	std_logic:='0';

	begin

	 
	 	 P(0)    <= pulsador(0) and not(pulsador(3));
       P(1)    <= pulsador(1) and not(pulsador(3));
       P(2)    <= pulsador(2) and not(pulsador(3));
       P(3)    <= pulsador(0) and pulsador(3);
       P(4)    <= pulsador(1) and pulsador(3);
       P(5)    <= pulsador(2) and pulsador(3);
		 
		rtdr:		rotador3d 	port map(P,xtal,enable,Xin,Yin,Zin,YR2M,ZR2M,l3);
		mnd:		mundo			port map(vsinc_o,hsinc_o,red_o,green_o,blue_o,rst,YR2M,ZR2M,xtal);
		ff1:		FF1b			port map(xtal,rst,l1);
		ff2:		FF1b			port map(xtal,l2,l3);
	 

end Behavioral;
-----------------------------------------------------------------------------------------------------
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;

--entity test is
--end test;

--architecture test of test is

--component Matiastop is
   --port(     
      pulsador       : in  std_logic_vector(3 downto 0);    
      xtal           : in  std_logic;
      enable         : in  std_logic;
      Xin            : in  std_logic_vector(15 downto 0);
      Yin            : in  std_logic_vector(15 downto 0);
      Zin            : in  std_logic_vector(15 downto 0);
	 	reset          : out std_logic;
		vsinc_o	 		    : out std_logic;
		hsinc_o	 		    : out std_logic;
		red_o		  		   : out std_logic;
	   green_o	 		    : out std_logic;
	   blue_o	  		    : out std_logic
   );
   end component;
   
   signal clk,e,rst,vs,hs,red,green,blue: std_logic:='0';
   signal pul: std_logic_vector(3 downto 0):="0000";
   signal Xin,Yin,Zin: std_logic_vector(15 downto 0):="0000000000000000";
   
   begin
   
   tt: Matiastop port map(pul,clk,e,Xin,Yin,Zin,rst,vs,hs,red,green,blue); 
   
   clk <= not clk after 10ns;
   e <= '0';
   rst <= '0';
   Xin <= "0010001101110111" after 20ns,"0010001110000101" after 40ns,"0010001110000101"after 60ns;
   Yin <= "0010010000110100" after 20ns,"0010010001011001" after 40ns,"0010010010010010"after 60ns;
   Zin <= "0000100000010111" after 20ns,"0000011110011001" after 40ns,"0000011110000000"after 60ns;
   
   
   
   end test;